Blog

HomePCB designWhat Is The Difference Between Series Circuit And Parallel Circuit ?

What Is The Difference Between Series Circuit And Parallel Circuit ?

What is a parallel signal and Serial signal?

To understand parallel signals and serial signals, let’s first understand the concepts of parallel communication (transmission) and serial communication (transmission).A parallel signal is a signal that is communicated in parallel, and a serial signal is a signal that is communicated in serial mode. Serial communication refers to the data transmission line in a single bit, a bit by bit in order delivery way, in the early days of the definition also said that only one data line, each clock pulse can only send a data mode.In a parallel communication in bytes (8 bits) data is at the same time by the end of the source to the destination in the 8 parallel transmission line, but also can be said to have a plurality of data lines (few is several), can send multiple data bits in each clock pulse (several parallel port to Send a few).

So early on serial communication and parallel communication understanding: a byte of data the same (8), serial communication to 8 from low to high order a bit transmission, and parallel communication with 8 line, so long as one can be transmitted in the past, the image of the said. Line (channel) compared to the Road, and arranged a few car can be said to be “parallel”, only a car opened as belonging to the “serial”.

Comparison, advantages and disadvantages of parallel communication and serial communication

Obviously, parallel communication is much faster, faster and less time-consuming than serial communication. But these are the theoretical understanding of early I/O rate is not high in the case, with the rapid development of information technology, before understanding the now outdated, because now is the era of high-speed serial signal (the subject).In high-speed state, crosstalk exists between several data lines of parallel port, while parallel port needs simultaneous sending and receiving of signal. Any delay of one data line will cause problems. The serial only one data line, there is no crosstalk between the signal lines, and serial can also use low-voltage differential signal, which can greatly improve its anti-interference.Therefore, a higher transmission rate can be achieved, although parallel data can be transmitted at a time, but the clock is much lower than the serial number, so the current serial transmission is the first choice for high-speed transmission.

From another point of view, parallel transmission has many ways, such as system synchronization (common clock) and source synchronous clock mode. First we look at the inherent problems of system synchronization, and the diagram below is a schematic diagram of the system synchronization in parallel transmission.

parallel signal and Serial signal-1

First, parallel signals are acceptable in the early days because of the need for multiple transmission paths. But Moore phenomenon makes compared with several decades ago the number of silicon chip circuit can produce a substantial increase, and the density of pin chip package technology and did not like the same density of silicon at the same speed increase, so the I/O pin package actually is expensive than silicon circuit, which means that for most of the chip pin feet more and more becomes unacceptable.

The second underlying problem is the demand for time series. From the above figure, the data is synchronized by chip 1 and is captured by the same clock synchronization on chip 2. The input data of chip 2 must be satisfied with the setting and holding time of the clock input relative to the chip. The detailed system synchronization timing model is shown in the following figure.

parallel signal and Serial signal-2

These build and hold times must be calculated with sufficient margin to allow clock allocation paths to be delayed to two chip differences, and to trigger and capture flip flops through the chip. Delays may vary depending on the chip process, voltage and temperature (PVT) conditions, and additional margin must be added to meet the worst case. For higher clock frequencies, it may be necessary to use the phase locked loop (PLL) in the chip to adjust the clock phase to compensate for on-chip clock allocation delays, and to adapt to variations in process, voltage, and temperature conditions. If the clock frequency is high enough, it is impossible to establish a system that can reliably transmit data through such a common clock bus.

Written by

The author didnt add any Information to his profile yet